This invention relates to a destuffing circuit and, in particular, to a destuffing circuit for use in combination with a demultiplexer of a digital multiplexing system.
The digital multiplexing system comprises transmitting equipment and receiving equipment. The transmitting equipment converts a plurality of low-speed pulse trains into a high-speed pulse stream. Each low-speed pulse train is delivered from a low-speed transmission line and comprises input data pulses. The transmitting equipment comprises a plurality of stuffing circuits. Each stuffing circuit adds stuffing pulses to the input data pulses to form a stuffed pulse train. The stuffed pulse train comprises stuffing pulses and input data pulses. Such stuffed pulse trains are multiplexed into a multiplexed pulse train by a multiplexer. The multiplexed pulse train includes control pulses which comprise frame synchronization pulses, stuffing appointment pulses, and so on. The multiplexed pulse train may be scrambled into a scrambled pulse train by a scrambler. Either the multiplexed pulse train or the scrambled pulse train is produced as the high-speed pulse stream. The high-speed pulse stream is delivered to the receiving equipment through a high-speed transmission line.
The receiving equipment converts the high-speed pulse stream into a plurality of reproduced low-speed pulse trains. More specifically, the receiving equipment may comprise a descrambler which descrambles the high-speed pulse stream into a descrambled pulse train if the high-speed pulse stream is the scrambled pulse train. The descrambled pulse train corresponds to the multiplexed pulse train. The multiplexed pulse train is demultiplexed into a plurality of demultiplexed pulse trains by a demultiplexer. Each demultiplexed pulse train comprises the stuffed pulse train and the control pulses. The demultiplexed pulse train is supplied to a destuffing circuit as an input pulse sequence. The demultiplexer comprises a destuffing control circuit which produces a data pulse timing signal. The data pulse timing signal supplied to the destuffing circuit in addition to the input pulse sequence. The destuffing circuit produces an output pulse sequence in which the stuffing and the control pulses are removed.
One of the digital multiplexing systems is the M13 digital multiplexing system as it is called in the art. The M13 digital multiplexing system converts 28 low-speed pulse trains of 1.544 Mbit/s into a high-speed pulse stream of 44.736 Mbit/s.
A known destuffing circuit is described in an article contributed by J. S. Mayo to The Bell System Technical Journal, Volume XLIV, No. 9 (November 1965), pages 1813 to 1841, under the title of "Experimental 224 Mb/s PCM Terminals." The destuffing circuit comprises a local signal producing arrangement responsive to the data pulse timing signal for producing a local signal and a destuffing arrangement responsive to the input pulse sequence for producing the output pulse sequence by using first through M-th timing sequence derived from the data pulse timing signal and first through M-th local sequence derived from the local signal where M represents a first predetermined number. The local signal producing arrangement is for analog processing a predetermined one of the first through the M-th timing sequences and a preselected one of the first through the M-th local sequences into the local signal, namely, is an analog phase-locked loop (PLL). The analogue PLL comprises a voltage-controlled crystal oscillator and a low-pass filter which comprises an analog amplifier and an analog filter. It is difficult to manufacture such a destuffing circuit as an integrated circuit. Accordingly, the destuffing circuit is high-priced and large-sized and has a higher consumption rate of electric power. The analog PLL has a driving power supply for driving the analog PLL. The driving power supply comprises two power sources which comprise a plus and a minus power source. Accordingly, the destuffing circuit has a number of parts.
Various digital PLL's are already known. By way of example, a digital PLL is described in an article which is published by Hirokazu Goto on International Conference Communication (San Francisco, Calif., June 8-10, 1978) and which is entitled "A DIGITAL PHASE-LOCKED LOOP FOR SYNCHRONIZING DIGITAL NETWORKS."
Another digital PLL is disclosed in U.S. Pat. No. 3,781,695 issued to Edward J. Jackson. It is difficult in the known destuffing circuit to substitute either a conventional digital PLL of Goto or that of Jackson for the analog PLL. This is because such a destuffing circuit falls out of synchronization when pulses of the data pulse timing signal are quiescent during presence of the stuffing and the control pulses in the input pulse sequence and introduces a quantization jitter in excess of the permissible jitter standard of the digital multiplexing system.